Intel today announced one of the industry’s first glass substrates for next-generation advanced packaging, planned for the latter part of this decade. This breakthrough achievement will enable the continued scaling of transistors in a package and advance Moore’s Law to deliver data-centric applications.
“After a decade of research, Intel has achieved industry-leading glass substrates for advanced packaging. We look forward to delivering these cutting-edge technologies that will benefit our key players and foundry customers for decades to come.”
–Babak Sabi, Intel senior vice president and general manager of Assembly and Test Development
Compared to today’s organic substrates, glass offers distinctive properties such as ultra-low flatness and better thermal and mechanical stability, resulting in much higher interconnect density in a substrate. These benefits will allow chip architects to create high-density, high-performance chip packages for data-intensive workloads such as artificial intelligence (AI). Intel is on track to deliver complete glass substrate solutions to the market in the second half of this decade, allowing the industry to continue advancing Moore’s Law beyond 2030.
By the end of the decade, the semiconductor industry will likely reach its limits on being able to scale transistors on a silicon package using organic materials, which use more power and include limitations like shrinkage and warping. Scaling is crucial to the progress and evolution of the semiconductor industry, and glass substrates are a viable and essential next step for the next generation of semiconductors.
As the demand for more powerful computing increases and the semiconductor industry moves into the heterogeneous era that uses multiple “chiplets” in a package, improvements in signaling speed, power delivery, design rules and stability of package substrates will be essential. Glass substrates possess superior mechanical, physical and optical properties that allow for more transistors to be connected in a package, providing better scaling and enabling assembly of larger chiplet complexes (called “system-in-package”) compared to organic substrates in use today. Chip architects will have the ability to pack more tiles – also called chiplets – in a smaller footprint on one package, while achieving performance and density gains with greater flexibility and lower overall cost and power usage.